In a large-scale integrated circuit (LSI) including a sequential circuit which operates in synchronization with a clock signal, the difference between two clock signals of different locations in the LSI (hereinafter called a clock skew) is one of the factors which reduce the operating frequency of the LSI directly. With the improvement in the speed of LSI, the ratio of the clock skew to one machine cycle is becoming large and the clock skew control and reduction are indispensable in order to achieve a high-speed operation of LSI. It is becoming impossible, therefore, to disregard a clock skew due to variations in the manufacturing process of a semiconductor chip (On-chip variation, OCV) with the advancement in miniaturization of devices and enlargement of a wafer diameter in semiconductor technology in recent years.
Occurrence of OCV in LSI is described in a non-patent reference by Nobuyuki Nishiguchi “a challenge to the process FRIENDLY design in a system LSI” [online], Jul. 7, 2006, Semiconductor Technology Academic Research Center, Inc., [Mar. 30, 2007 search]—Internet <URL: http://www.starc.jp/download/forum2006/03-nishiguchi.pdf>. As shown in Slide 20 of this reference, there are two components of OCV, one is a random component produced at random within a chip, the other a systematic component having a spatial correlation within a chip, and these components are combined and observed as an on-chip variation.
A conventional technology is disclosed in JP-A-Hei4(1992)-076610, of distributing clocks taking into account of the characteristics variation in a chip. FIG. 2 shows a clock skew adjustment method disclosed in JP-A-Hei4(1992)-076610. In FIG. 2 an LSI chip 1100 is divided into three clock supplying regions, 1140, 1141, and 1142 and the clock phases near boundaries are compared by a phase comparator 1131 disposed near the boundary of the regions, and the phases are matched by variable delay circuits 1110 and 1120 arranged upstream in the clock tree scheme. Then, on the basis of the clock of the region 1141 thus matched as a reference, the clock of the non-adjusted region 1142 adjacent to the region 1141 is compared with the reference by a phase comparator 1132 and adjusted by a variable delay circuit 1122.